作业帮verilog语句理解问题reg [11:0]row_cntreg [31:0]append_log[11:0]ROW_NUMif(row_cnt==ROW_NUM&&(~append_log[30]&append_log[31]==1'b1))row_add_en
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![verilog语句理解问题reg [11:0]row_cntreg [31:0]append_log[11:0]ROW_NUMif(row_cnt==ROW_NUM&&(~append_log[30]&append_log[31]==1'b1))row_add_en](/uploads/image/z/6844944-48-4.jpg?t=verilog%E8%AF%AD%E5%8F%A5%E7%90%86%E8%A7%A3%E9%97%AE%E9%A2%98reg+%5B11%3A0%5D%05row_cntreg+%5B31%3A0%5D%05append_log%5B11%3A0%5D%05ROW_NUMif%28row_cnt%3D%3DROW_NUM%26%26%28%7Eappend_log%5B30%5D%26append_log%5B31%5D%3D%3D1%27b1%29%29%05%05row_add_en)
verilog语句理解问题reg [11:0]row_cntreg [31:0]append_log[11:0]ROW_NUMif(row_cnt==ROW_NUM&&(~append_log[30]&append_log[31]==1'b1))row_add_en
verilog语句理解问题
reg [11:0]row_cnt
reg [31:0]append_log
[11:0]ROW_NUM
if(row_cnt==ROW_NUM&&(~append_log[30]&append_log[31]==1'b1))
row_add_en
verilog语句理解问题reg [11:0]row_cntreg [31:0]append_log[11:0]ROW_NUMif(row_cnt==ROW_NUM&&(~append_log[30]&append_log[31]==1'b1))row_add_en
row_cnt的值等于ROW_NUM,并且append_log的bit30为0,append_log的bit31为1,才满足if条件.这时row_add_en这个寄存器输出变成1.
当然在数字电路中if中条件都是用与门和非门组成.